8Gb/s/pin 4-level Simultaneous Bidirectional I/O

The trend in VLSI towards speed and power. To allow this tremendous increase in circuit size, geometries are being aggressively scaled down. This downscale increases the need to communicate with the external world such as storage, display, or any further data processing. Also, the longer word size and the higher data rate in the chip interface lead to increase in the number of I/O pins in a unit area of a package and the power dissipation as well.

Pin count increases as the number of circuit increases

In chip-to-chip communications, the topology of the communications affects to the performance of the communication links. Multidrop is a configuration in which components are all connected to the same set of communication wires. It polls data in sequence over one communication wire that results in a cheaper solution at the expense of response time.

Point-to-point dedicates one communication line between two chips. It is usually preferred for the high speed links that require high reliability even though it comes with large number of I/O. In a point-to-point link, increasing the bandwidth per wire enhances system performance due to limited number of pins. Simultaneous Bidirectional (SBD) signaling was previously introduced to allow simultaneous data transmission in two directions over one wire, doubling the effective bandwidth per pin over a point-to-point unidirectional transmission. The multi-level SBD I/O enhances data rate over SBD I/O at the expense of less voltage distance.

This research is develping a high speed multi-level simultaneous bi-directional I/O. When an I/O switches data, it consumes large current to drive output loads, which causes simultaneous switching noise (SSN) induced by parasitics. A differential scheme is one of the best solutions that makes the total sum of AC currents ideally zero. To increase data rate, firstly,  calibration is considered for the impedance mismatch between the two chips which reduces the voltage margin and for the mismatch between voltage references and incoming signal which degrades Symbol Error Rate (SER). Also, a band-gap reference is used to reduce the effects of supply voltage fluctuation, temperature variation, and chip-to-chip mismatches. Secondly, in an I/O, a large size of current switches limits the bandwidth. A latched differential current switching scheme and pre-emphasis enhance speed in the transmitter. In the receiver end, de-emphasis to a voltage references and a clocked comparator are applied for the higher symbol rate. Simulation based on 0.18um CMOS process show that the proposed design achieves data rate up to 8-Gb/s/pin at the power consumption of 46.8mW with 1.8V power supply.

Eye diagram at the receiver